3-1 tm file number 2786.4 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright intersil corporation 2000 HSP9501 programmable data buffer the HSP9501 is a 10-bit wide programmable data buffer designed for use in high speed digital systems. two different modes of operation can be selected through the use of the modsel input. in the delay mode, a programmable data pipeline is created which can provide 2 to 1281 clock cycles of delay between the input and output data. in the data recirculate mode, the output data path is internally routed back to the input to provide a programmable circular buffer. the length of the buffer or amount of delay is programmed through the use of the 11-bit length control input port (lc0- 10) and the length control enable ( lcen). an 11-bit value is applied to the lc0-10 inputs, lcen is asserted, and the next selected clock edge loads the new count value into the length control register. the delay path of the HSP9501 consists of two registers with a programmable delay ram between them, therefore, the value programmed into the length control register is the desired length - 2. the range of values which can be programmed into the length control register are from 0 to 1279, which in turn results in an overall range of programmable delays from 2 to 1281. clock select logic is provided to allow the use of a positive or negative edge system clock as the clk input to the HSP9501. the active edge of the clk input is controlled through the use of the clksel input. all synchronous timing (i.e., data setup, hold, and output delays) are relative to the clock edge selected by clksel. an additional clock enable input ( clken) provides a means of disabling the internal clock and holding the existing contents temporarily. all outputs of the HSP9501 are three-state outputs to allow direct interfacing to system or multi-use busses. the HSP9501 is recommended for digital video processing or any applications which require a programmable delay or circular data buffer. features dc to 32mhz operating frequency programmable buffer length from 2 to 1281 words supports data words to 10 bits clock select logic for positive or negative edge system clocks data recirculate or delay modes of operation expandable data word width or buffer length three-state outputs ttl compatible inputs/outputs low power cmos applications sample rate conversion data time compression/expansion software controlled data alignment programmable serial data shifting audio/speech data processing video/image processing video/image processing 1-h delay line of 910 ntsc, 1135 pal or 1280 samples: - high resolution monitor delay line - comb filter designs - progressive scanning display - tv standards conversion - image processing ordering information part number temp. range ( o c) package pkg. no. HSP9501jc-25 0 to 70 44 ld plcc n44.65 HSP9501jc-32 0 to 70 44 ld plcc n44.65 HSP9501jc-2596 0 to 70 44 ld plcc tape and reel n44.65 data sheet january 1999
3-2 pinout 44 lead plcc top view block diagram clksel clk lc2 lc3 lc4 lc5 modsel nc nc lcen clk en do9 oe lc0 lc1 lc10 lc9 lc8 lc7 lc6 di9 nc 40 65 32144434241 4 18 19 20 21 22 23 24 25 26 27 28 7 17 16 15 12 13 14 9 10 11 8 38 37 39 35 34 33 36 31 30 29 32 do0 do1 do2 do3 do4 gnd do5 do6 do7 do8 v cc di0 di1 di2 di3 di4 gnd di5 di6 di7 di8 v cc modsel mux clock generator clksel clk clken 11 register register en 11 10 10 lc0 -10 oe 10 do0-9 10 di 0 -9 10 10 10 lcen register programmable delay ram 0-1279 delays register HSP9501
3-3 pin descriptions name pin number type description v cc 12, 34 the +5v power supply pin. a 0.1 f capacitor between the v cc and gnd pin is recommended. gnd 13, 33 the device ground. clk 1 i input clock. this clock signal is used to control the data movement through the programmable buffer. it is also the signal which latches the input data, length control word and mode select. input setup and hold times with respect to the clock must be met for proper operation. dio-9 27, 29-32, 35-39 i data inputs. this 10-bit input port is used to provide the input data. when modsel is low, data on the di0-9 inputs is latched on the clock edge selected by clksel. do0-9 7-11, 14-18 o data outputs. this 10-bit port provides the output data from the internal delay registers. data latched into the di0-9 inputs will appear at the do0 9 outputs on the nth clock cycle, where n is the total delay programmed. lc0-10 20-26, 41-44 i length control inputs. these inputs are used to specify the number of clock cycles of delay between the di0-9 inputs and the do0-9 outputs. an integer value between 0 and 1279 is placed on the lc0-10 inputs, and the total delay length (n) programmed is the lc0-10 value plus 2. in order to properly load an active length control word, the value must be presented to the lc0-10 inputs and lcen must be asserted during an active clock edge selected by clksel. lcen 6 i length control enable. lcen is used in conjunction with lc0-10 and clk to load a new length control word. an 11-bit value is loaded on the lc0-10 inputs, lcen is asserted, and the next selected clock edge will load the new count value. since this operation is synchronous, lcen must meet the specified setup/hold times with respect to clk for proper operation. oe 19 i output enable. this input controls the state of the do0-9 output port. a low on this control line enables the port for output. when oe is high, the output drivers are in the high impedance state. internal latching or transfer of data is not affected by this input. modsel 40 i mode select. this input is used to control the mode of operation of the HSP9501. a low on modsel causes the device to latch new data at the di0-9 inputs on every clock cycle, and operate as a programmable pipeline register. when modsel is high, the HSP9501 is in the recirculate mode, and will operate as a programmable length circular buffer. this control signal may be used in a synchronous fashion during device operation, however, care must be taken to ensure the required setup/hold times with respect to clk are met. clksel 5 i clock select control. this input is used to determine which edge of the clk signal is used for controlling all internal events. a low on clksel selects the negative going edge, therefore, all setup, hold, and output delay times are with respect to the negative edge of clk. when clksel is high, the positive going edge is selected and all synchronous timing is with respect to the positive edge of the clk signal. clken 2 i clock enable. this control signal can be used to enable or disable the clk input. when low, the clk input is enabled and will operate in a normal fashion. a high on clken will disable the clk input and will ?old'' all internal operations and data. this control signal may also be used in a synchronous fashion, however, setup and hold requirements with respect to clk must be met for proper device operation. this signal takes effect on the clock following the one that latches it in. HSP9501
3-4 functional description the HSP9501 is a 10-bit wide programmable length data buffer. the length of delay is programmable from 2 to 1281 delays in single delay increments. data into the delay line may be selected from the data input bus (di0-9) or as recirculated output, depending on the state of the mode select (modsel) control input. mode select the modsel control pin selects the source of the data moving into the delay line. when modsel is low, the data input bus (di0-9) is the source of the data. when modsel is high, the output of the HSP9501 is routed back to the input to form a circular buffer. the modsel control line is latched at the input by the clk signal. the edge which latches this control signal is deter- mined by the clksel control line. in either case, the modsel line is latched on one edge of the clk signal with the following edge moving data into and through the HSP9501. refer to the functional timing waveforms for speci? timing references. clock select logic the clock select logic is provided to allow the use of positive or negative edge system clocks. the active edge of the clk input to the HSP9501 is controlled through the use of the clksel input. when clksel is low, the negative going edge of clk is used to control all internal operations. a high on clksel selects the positive going edge of clk. all synchronous timing (i.e., setup, hold and output propagation delay times are relative to the clk edge selected by clksel. functional timing waveforms for each state of clksel are provided (refer to timing waveforms for details). delay path control the HSP9501 buffer length is programmable from 2 to 1281 data words in one word increments. the minimum number of delays which can be programmed is two, consisting of the input and output buffer registers only. the length control inputs (lc0-10) are used to set the length of the programmable delay ram which can vary in length from 0 to 1279. the total length of the HSP9501 data buffer will then be equal to the programmed value on lc0-10 plus 2. the programmed delay is established by the 11-bit integer value of the lc0-10 inputs with lc-10 as the msb and lc0 as the lsb. for example, programs a length value of 2 6 + 2 0 = 65. the total length of the delay will be 65 + 2 or 67 delays. table 1 indicates several programming values. the decimal value placed on lc0-10 must not exceed 1279. controlled operation with larger values is not guaranteed. values on lc0-10 are latched on the clk edge selected by the clksel control line, when lcen is active. lc0-10 and lcen must meet the speci?d setup and hold times relative to the selected clk edge for proper device operation. lc10 9 8 7 6 5 4 3 2 1 lc0 0 000100000 1 table 1. length control programming examples lc10 2 10 lc9 2 9 ls8 2 8 lc7 2 7 lc6 2 6 lc5 2 5 lc4 2 4 lc3 2 3 lc2 2 2 lc1 2 1 lc0 2 0 programmed length total length n 0 0000000000 0 2 0 0001110110 118 120 0 1100101000 808 810 1 0 0 0 0 0 1 1 0 0 1 1049 1051 1 0 0 1 1 1 1 1 1 1 1 1279 1281 HSP9501
3-5 absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0v input, output or voltage applied . . . . . . . .gnd -0.5v to v cc +0.5v operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 o c to 70 o c voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75v to 5.25v thermal resistance (typical, note 1) ja ( o c/w) plcc package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45.2 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (plcc - lead tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. dc electrical speci?ations v cc = 5.0v +5%, t a = 0 o c to 70 o c, commercial parameter symbol test conditions min max units logical one input voltage v ih v cc = 5.25v 2.0 - v logical zero input voltage v il v cc = 4.75v - 0.8 v output high voltage v oh i oh = -4ma v cc = 4.75v 2.4 - v output low voltage v ol i ol = +4.0ma v cc = 4.75v - 0.4 v input leakage current i i v in = gnd or v cc v cc = 5.25v -10 10 a output leakage current i o v out = gnd or v cc = 5.25v -10 10 a standby current i ccsb v in = v cc or gnd, v cc = 5.25v, note 3 - 500 a operating power supply current i ccop f = 25mhz, v in = v cc or gnd v cc = 5.25v, notes 2, 3 - 125 ma input capacitance c in freq = 1mhz, v cc = open, all measurements are referenced to device gnd -10 pf output capacitance c o -10 pf ac electrical speci?ations v cc = 5.0v 5%, t a = 0 o c to +70 o c, commercial, (note 5) parameter symbol -32 -25 units notes min max min max clock period t cp 31 - 40 - ns - clock pulse width high t pwh 12 - 15 - ns - clock pulse width low t pwl 12 - - 15 ns - data input setup time t ds 10 - 12 - ns - data input hold time t dh 2-2-ns- output enable time t ena - 20 - 25 ns - output disable time t dis - 24 - 25 ns note 4 clken to clock setup t es 10 - 12 - ns - clken to clock hold t eh 2-2-ns- lc0-10 setup time t ls 10 - 13 - ns - lc0-10 hold time t lh 2-2-ns- lcen to clock setup t les 10 - 13 - ns - HSP9501
3-6 test load circuit note: includes stray and jig capacitance. lcen to clock hold t leh 2-2-ns- modsel setup time t ms 10 - 13 - ns - modsel hold time t mh 2-2-ns- clock to data out t out - 16 - 22 ns - output hold from clock t oh 4-4-ns- rise, fall time t rf - 6 - 6 ns note 4 notes: 2. power supply current is proportional to operating frequency. typical rating for i ccop is 5ma/mhz. 3. output load per test load circuit with switch open and c l = 40pf. 4. controlled by design or process parameters and not directly tested. characterized upon initial design and after major process and/or design changes. 5. ac testing is performed as follows: input levels: 0v and 3.0v, timing reference levels = 1.5v, input rise and fall times driven at 1ns/v, output load c l = 40pf. ac electrical speci?ations v cc = 5.0v 5%, t a = 0 o c to +70 o c, commercial, (note 5) (continued) parameter symbol -32 -25 units notes min max min max equivalent circuit c l (note) i oh 1.5v i ol dut switch s1 open for i ccsb and i ccop s 1 HSP9501
3-7 timing waveforms figure 1. functional timing (clksel = low) figure 2. clen timing (clksel = low) figure 3. output rise and fall times figure 4. length control timing (clksel = low) t ms t pwl t pwh t dh t ds t dis t ena t out 1.7 1.3 t mh clk modsel oe di 0 -9 do 0 -9 t oh t cp clk internal clock clken t es t eh t es t rf t rf 2.0v 0.8v 2.0v 0.8v clk lcen t les t ls t leh t lh lc0 -10 HSP9501
3-8 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com figure 5. functional timing (clksel = high) figure 6. clken timing (clksel = high) figure 7. length control timing (clksel = high) timing waveforms (continued) t ms t dh t ds t dis t ena t out 1.7 1.3 t mh clk modsel oe di 0 -9 do 0 -9 t oh t cp t pwl t pwh internal clock clken t es t es clk t eh lcen t les t ls t leh t lh clk lc 0 -10 HSP9501
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